A transistor is a semiconductor device used to amplify and switch electronic signals and electrical power. It is composed of semiconductor material with at least three terminals for connection to an external circuit. The terminals are a gate, a source, a drain, and a body. Voltage is transmitted from the source to the drain when the transistor is on, which is controlled via a voltage applied to the gate. A complimentary metal-oxide-semiconductor (CMOS) is a technology to make circuits including semiconductor transistors.
Two associated parameters of both P-type and N-type CMOS semiconductor transistors are threshold voltage, the voltage needed between the gate of a transistor and its source to turn it on, and saturation current, the current flowing through the source of a CMOS device with the gate voltage at maximum drive with respect to the source (VDD) and the voltage applied across the drain and source equal to VDD. Both parameters indicate the drive strength of the CMOS transistor. These two transistor parameters, the threshold voltage and the saturation current, are reflected in the speed of circuits in which such transistors are used as basic components.
CMOS transistors, P-type and N-type undergo a change, typically a degradation, in their threshold voltage and saturation current over time. This degradation in the threshold voltage and saturation current of a transistor takes the form of an increase in the magnitude of the threshold voltage and a decrease in the magnitude of the saturation current. There are several physics based phenomena that cause such degradation.
One phenomenon is elevated electric fields between the gate of the transistor and its drain, known as hot carrier injection (HCI) resulting in a permanent shift in threshold voltage. Another phenomenon is “biased thermal instability” (BTI) that causes partially recoverable degradation in the threshold voltage of the transistor.
BTI is highly dependent on several factors, including temperature, total switching time, and the switching behavior of the transistor, also known as the switching duty cycle. The BTI induced change in the threshold voltage and saturation current of P-type transistors (P-transistor) referred to as “negative bias thermal instability” (NBTI). This is an issue in P-type transistors because they almost always operate with negative gate-to-source voltage. It is also an issue in N-type transistors when a negative bias is applied to the gate.
The NBTI phenomenon is a partially reversible process. This means that when the applied source-to-gate bias is removed, the transistor is capable of recovering part of the change in threshold voltage and in saturation current brought about by the applied bias. The amount of recovery is heavily dependent on the duration of the absence of any source-to-gate bias.
Modeling NBTI is important for accurate circuit simulation. Because of the partial recovery aspect of NBTI, the accuracy of modeling depends on the amount of time between the application of the source-to-gate bias and the measurement of the magnitude of change in the threshold voltage and saturation current.
FIG. 1 illustrates a standard NBTI test setup representing the current state of the art. A bench tester 10 applies an external voltage bias of zero volts to the gate of a P-transistor P10 and measures the current flowing through the transistor. Then the P-transistor P10 is stressed through applying a stress voltage Vg at the gate of the P-transistor P10 and through applying a voltage Vdd, equal to the source voltage of P-transistor P10, the drain of the P-transistor P10 to keep the potential between the source and the drain of P-transistor P10 at zero during the stress phase of the test as shown in waveform 20. After the stress phase is complete, the bench tester 10 releases the applied voltages to the gate and drain of P-transistor P10 and re-applies a bias of zero volts to the gate of the P-transistor P10. The bench tester 10 then measures the new value of the current flowing through the transistor. There is usually a delay between the stress phase and the measure phase determined by the tester limitations and specifications.